The present invention relates to a communication testing circuit, an electronic device, a receiving circuit, a transmitting circuit, a semiconductor integrated circuit, and a wafer.
In consumer electronics, particularly digital AV devices that handle high-volume video data such as full high definition, the shift from low-speed parallel communication to high-speed serial communication is accelerated between LSIs (large-scale integrations) of the same substrate, between LSIs of different substrates, between devices or the like.
Compatibility between high quality and low cost is important in this area where mass production is done, and in the field of high-speed serial communication also, it is required to implement a system that prevents defective products from reaching the market at low cost.
As related techniques, the following methods are generally performed.
Method 1: As a testing method at the transmitting end, quantitative evaluation of a timing margin is performed by waveform measurements using an oscilloscope.
Method 2: As a testing method at the receiving end, quantitative evaluation of a timing margin is performed by jitter tolerance measurements using a data generator with a jitter generation function (cf. Japanese Unexamined Patent Publication No. 2005-233933).
Method 3: Testing of a serial communication part is conducted by incorporating a pseudo-random binary sequence generator into a circuit at the transmitting end and checking the presence or absence of a data communication error in a pseudo-random pattern detector incorporated in a circuit at the receiving end.